1. Field of the Invention
The present invention relates to a zero crossing detector and, more particularly, to a high speed, low-power, pipelined zero crossing detector that utilizes carry save adders.
2. Description of the Related Art
Zero crossing detectors are useful in a wide variety of applications, including set point controllers and clock recovery circuits. A zero crossing detector typically utilizes an adder array, which has sum and carry outputs, to add together a number of signed binary numbers. The resulting sum and carry outputs of the adder array can then be examined to determine whether or not a zero crossing has occurred.
In many zero crossing applications, the signed binary numbers input to the adder array are only a few bits in length. For example, each signed binary number input to the adder array can be limited to two bits which, in turn, can be used to represent the numbers 0, +1, and −1, e.g., 00=0, 01=1, 11=−1, and 10=(not allowed).
Clock recovery applications provide a good example of the use of signed binary numbers with a limited number of bits. In a clock recovery application, a user must determine whether or not the rising edge of the clock is centered in the middle of the input data transition, or whether the rising clock edge is early or late. These three possibilities can be represented by the three numbers 0, −1, and +1 which, in turn, require two bits.
FIG. 1 shows a block diagram that illustrates a prior-art, zero crossing detector 100. As shown in FIG. 1, zero crossing detector 100, which is suitable for use in clock recovery applications, has four two-bit binary number inputs. The four two-bit binary number inputs include inputs W0 and W1, X0 and X1, Y0 and Y1, and Z0 and Z1.
Each two-bit input pair W0/W1, X0/X1, Y0/Y1, and Z0/Z1 receives an input signal pair WT0/WT1, XT0/XT1, YT0/YT1 and ZT0/ZT1, respectively. The input signal pairs WT0/WT1, XT0/XT1, YT0/YT1 and ZT0/ZT1, in turn, each have logic states that represent one of three signed numbers, 0, +1, and −1, e.g., 00=0, 01=1, 11=−1, and 10=(not allowed). The inputs W0, X0, Y0 and Z0 represent the least significant bits, while the inputs W1, X1, Y1 and Z1 represent the most significant bits.
In addition, zero crossing detector 100 also has a clock input CLK that receives a clock signal CS used to accumulate the input values, and a clear input CLR that receives a clear signal CLS used to reset detector 100. Zero crossing detector 100 also has an up output UP that generates an up signal US, and a down output DWN that generates a down signal DS.
In operation, zero crossing detector 100 only asserts the up signal US on the up output UP when a positive zero crossing is detected, and the down signal DS on the down output DWN when a negative zero crossing is detected. If no zero crossing is detected, both the up and down signals US and DS remain inactive.
The maximum and minimum binary values that can be placed on each input pair W0/W1, X0/X1, Y0/Y1, and Z0/Z1 are the same, +1 and −1, respectively. Thus, when the binary values on the input pairs W0/W1, X0/X1, Y0/Y1 and Z0/Z1 are each equal to the maximum value, the maximum positive sum is +4.
Similarly, when the binary values on the input pairs W0/W1, X0/X1, Y0/Y1 and Z0/Z1 are each equal to the minimum value, the minimum negative sum is −4. In addition, the binary values on the input pairs W0/W1, X0/X1, Y0/Y1 and Z0/Z1 can also sum to zero and positive and negative values in between.
As a result, zero crossing detector 100 can receive the following nine signed values:                −4, −3, −2, −1, 0, +1, +2, +3, and +4.        
In order to accommodate the nine signed values shown above, zero crossing detector 100 must have at least four bits. However, the zero crossing logic can be designed to detect two-bit zero crossings, three-bit zero crossings and four-bit zero crossings.
FIGS. 2A-2C show three circular state diagrams that illustrate the operation of three prior-art, zero crossing detectors. FIG. 2A shows the operation of a two-bit zero crossing detector 200A, FIG. 2B shows the operation of a three-bit zero crossing detector 200B, and FIG. 2C shows the operation of a four-bit zero crossing detector 200C.
As shown in FIGS. 2A-2C, the circular state diagrams resemble automobile tachometers and, as a result, can be referred to as “RPM counters”. The two-bit RPM counter shown in FIG. 2A has only four states: 0, +1, −2 and −1, each of which can be “pointed to” by the arrow emanating from the center of the circle. In addition, the zero crossing line (ZCL) is located between the value −1 and the value 0.
In operation, when one of the positive input values +1, +2, +3 or +4 is input to zero crossing detector 100, the arrow will rotate in the positive direction (clockwise) a number of steps as defined by the positive input value. Similarly, when one of the negative input values −1, −2, −3 or −4 is input to zero crossing detector 100, the arrow will rotate in the negative direction (counterclockwise) a number of steps as defined by the negative input value.
For example, when the arrow in FIG. 2A is pointing to +1 and zero crossing detector 100 receives a value of +3, zero crossing detector 100 rotates the arrow forward by three steps, causing it to land on the value zero. In so doing, the arrow sweeps past the ZCL in the positive (clockwise) direction, thereby generating a positive zero crossing.
Similarly, when the arrow in FIG. 2A is pointing to +1 and zero crossing detector 100 receives a value of −3, zero crossing detector 100 rotates the arrow backward by three steps, causing it to land on the value −2. In so doing, the arrow sweeps past the ZCL in the negative (counterclockwise) direction, thereby generating a negative zero crossing.
Furthermore, when the arrow in FIG. 2A is pointing to +1 and zero crossing detector 100 receives a value of −1, zero crossing detector 100 rotates the arrow backward by one step, causing it to land on the value zero. In so doing, the arrow does not sweep past the ZCL in the negative (counterclockwise) direction, and thus no zero crossing occurs.
Similarly, when the arrow in FIG. 2A is pointing to +1 and zero crossing detector 100 receives a value of +1, zero crossing detector 100 rotates the arrow forward by one step, causing it to land on the value −2. In so doing, the arrow does not sweep past the ZCL in the positive (clockwise) direction, and thus no zero crossing occurs.
The three-bit and four-bit zero crossing detectors 200B and 200C shown in FIGS. 2B and 2C operate in exactly the same manner as two-bit zero crossing detector 200A operates, except that detectors 200B and 200C have more states. As a result of having more states, detectors 200B and 200C generate zero crossings less frequently.
For example, if zero crossing detector 200A receives the maximum or minimum input value of +4 or −4, respectively, a positive or negative zero crossing always occurs no matter where the arrow is initially pointing. However, if zero crossing detector 200C is initially pointing to a value between +4 and −5, and detector 200C receives the maximum or minimum input value of +4 or −4, respectively, no zero crossing occurs.
FIG. 3 shows a block diagram that further illustrates prior-art, zero crossing detector 100. As shown in FIG. 3, detector 100 includes an adder array 310, an accumulator register 312, and a zero crossing logic block 314. As further shown in FIG. 3, the input pairs W0/W1, X0/X1, Y0/Y1 and Z0/Z1 are inputs to adder array 310 and, as noted above, each receives a signed two-bit number that represents the numbers 0, +1, and −1 (the value −2 is prohibited).
Furthermore, adder array 310 also has four sum inputs SUM0-SUM3 that receive four sum signals M0, M1, M2 and M3, respectively. The four sum signals M0-M3 are generated by accumulator register 312 and represent the current binary value held in accumulator register 312. In addition, adder array 310 also generates four sum outputs S0, S1, S2 and S3 that produce four sum signals SM0, SM1, SM2 and SM3, respectively, and four carry outputs CY0, CY1, CY2 and CY3 that generate four carry output signals C0, C1, C2 and C3, respectively.
Referring to FIG. 3, adder array 310 adds up five numbers: The four signed two-bit input numbers WT0/WT1, XT0/XT1, YT0/YT1, ZT0/ZT1, and the signed 4 bit number M0-M3 from accumulator register 312. Adder array 310 then drives the binary value of the sum signals SM0-SM3 on the sum outputs S0-S3 to accumulator register 312.
Furthermore, adder array 310 also drives the binary values of the sum and carry signals SM0-SM3 and C0-C3 on the sum and carry outputs S0-S3 and CY0-CY3 to the zero crossing logic block 314. Zero crossing logic block 314 then uses these signals to generate the zero crossing signals up and down, US and DS. As described above, the up signal US is asserted when a positive zero crossing is detected, while the down signal DS is asserted when a negative zero crossing is detected. If no zero crossing is detected, the up and down signals US and DS remain inactive.
FIG. 4 shows a block diagram that illustrates prior-art, adder array 310. As shown in FIG. 4, adder array 310 has a number of adder cells U, including half adder cells HA and full adder cells FA, that are arranged in rows and columns. Each half adder cell HA has first and second inputs A and B, a sum output S, and a carry output CO. Furthermore, each full adder cell FA is similar to half adder cell HA, except that each full adder cell FA also includes a carry input CI.
In the FIG. 4 example, adder array 310 has 16 adder cells U00-U03, U10-U13, U20-U23 and U30-U33 that are arranged in four rows, ROW0, ROW1, ROW2 and ROW3 respectively. Each row of cells, in turn, has one half adder cell HA (representing the least significant bit) and three full adder cells FA.
In operation, the adder cells U00-U03 in first row ROW0 add together the binary value on the inputs W0/W1 with the binary value on the inputs X0/X1. The sum of the binary values on the inputs W0/X0 and W1/X1 is then added to the binary value on the inputs Y0/Y1 by the adder cells U10-U13 in the second row ROW1.
Similarly, the sum of the W, X, and Y inputs is next added to the binary value on the inputs Z0/Z1 by the adder cells U20-U23 in the third row ROW2. Finally, the sum of the W, X, Y, and Z inputs is then added to the binary value on the sum inputs SUM0-SUM3, as represented by the sum signals M0-M3, by the adder cells U30-U33 in the fourth row ROW3. Adder array 310 generates the sum of its 5 input numbers on the four sum outputs S0, S1, S2 and S3, and on its four carry outputs CY0, CY1, CY2 and CY3.
Although adder array 310 can be used for low to medium speed applications, one drawback of adder array 310 is that it is too slow to be used in high speed applications. The primary reason for this is that all of the carry outputs of the adder cells U in one row must become valid before all of the inputs in the next row can become valid.
For example, as shown in FIG. 4, the input B of full adder U11 can not become valid until the output S of full adder U01 becomes valid, which can not become valid until the carry input CI of adder cell U01 becomes valid. Similarly, the input B of full adder U12 can not become valid until the output S of full adder U02 becomes valid, which can not become valid until the carry input CI of adder cell U02 becomes valid.
Thus, to be used in high speed applications, the horizontal carry propagation delay must be reduced. (The horizontal propagation delay in the last row ROW3 can not be eliminated because the zero crossing logic requires the values that are generated by the sum outputs S0-S3 and the carry outputs CY0-CY3 by the last row ROW3 of adder cells U30-U33.)
FIG. 5 shows a block diagram that illustrates a prior-art adder array 500. Adder array 500 is similar to adder array 310 and, as a result, utilizes the same reference numerals to designate the structures that are common to both arrays. As shown in FIG. 5, adder array 500 differs from adder array 310 in that adder cells U03 and U13 have been eliminated, and adder cell U23 has been reduced from a full adder to a half adder.
The above simplifications can be made because, when the binary values on the inputs W0/W1 and X0/X1 are summed together in first row ROW0, the resulting sum can only range from −2 to +2. Since this range only contains five values, it can be represented by only three bits with three adder cells U. In addition, the adder cells U10-U12 in second row ROW1 add the binary value on the inputs Y0/Y1 to the sum of the W and X inputs. Thus, the sum output from second row ROW1 can only range from −3 to +3. Since this range only contains 7 values, it can also be represented by only three bits with three adder cells U.
Furthermore, the adder cells U20-U23 in third row ROW2 add the binary value on the inputs Z0/Z1 to the sum of the W, X, and Y inputs. Thus, the sum output from third row ROW2 can range from −4 to +4. Since this range contains 9 values, it must be represented by four adder bits with four adder cells U. However, as shown in FIG. 5, the most significant adder cell U23 in third row ROW2 can be changed from a full adder to a half adder because it only needs to sum two inputs.
Although simplified adder array 500 is faster than adder array 312, adder array 500 remains too slow for many high speed applications. As a result, there is a need for a faster adder array.